P0_1/MCPWM1_BKIN2/UART0_RXD/SPI0_CSN/TIM4_CH1/CAN_TX/EXTI1/5VT1P0_2/CMP5_OUT/MCPWM1_BKIN3/UART0_TXD/CAN_RX/CMP5_IP0/WAKE0/EXTI2/5VT2VDD3P0_10/MCPWM1_CH0P/SPI0_CSN/TIM1_CH1/EFLS_DAT[2]/CMP4_IN/SWDIOTMS/5VT4P0_11/MCPWM1_CH1N/UART1_RXD/SPI0_DI/SCL1/TIM4_CH1/EFLS_DAT[3]/CMP4_IP0/TDI/5VT5P0_6/RST_n/5VT6P0_7/OSC_OUT7VSS8P0_8/TIM1_Z/EFLS_DAT[0]/OSC_IN9AVDD10P0_5/CMP5_OUT/HALL1_IN0/MCPWM0_BKIN3/UART0_TXD/SPI0_CLK/SCL0/TIM0_CH1/TIM2_Z/ADC_TRIGGER0/ADC2_CH12/CMP5_IP3/WAKE3/EXTI5/5VT11P1_8/MCPWM0_CH3P/UART2_RXD/SPI1_CLK/TIM0_CH0/TIM2_Z/CAN_TMR/5VT12P0_12/MCPWM1_CH1P/UART1_TXD/SPI0_DO/SDA1/TIM4_CH0/CAN_TMR/EFLS_CSN/CMP4_IP1/SWCLKTCLK/5VT13P0_13/MCPWM1_CH2N/UART0_TXD/SPI1_CSN/TIM4_CH0/CAN_TX/CMP4_IP2/WAKE4/EXTI6/TDO/5VT14P0_14/CLK/MCPWM1_CH2P/UART0_RXD/SPI1_DI/SCL0/CAN_RX/CMP4_IP3/EXTI715P1_0/MCPWM1_CH3P/UART0_TXD/SPI1_DO/SDA0/TIM0_Z16P1_5/MCPWM0_CH2N/UART1_RXD/SPI0_DI/SCL1/TIM4_CH1/TIM3_Z/CAN_TX/EXTI9/5VT17P1_6/MCPWM0_CH2P/UART1_TXD/SPI0_DO/SDA1/TIM4_CH0/CAN_RX/5VT18P1_9/MCPWM0_BKIN0/UART2_TXD/SPI1_DO/SDA0/TIM0_CH1/TIM2_CH0/ADC_TRIGGER2/CAN_TX/5VT19P1_10/MCPWM0_BKIN1/UART2_RXD/SPI1_DI/SCL0/TIM0_CH0/TIM2_CH1/ADC_TRIGGER1/CAN_RX/5VT20P1_11/MCPWM0_BKIN2/UART2_TXD/SPI0_DO/SDA0/TIM0_CH1/OPA5_IN/WAKE5/EXTI1121P1_12/MCPWM1_CH3N/UART2_RXD/SPI0_DI/SCL0/TIM1_CH0/OPA5_IP/EXTI1222AVDD23P2_2/MCPWM1_BKIN0/EFLS_DAT[2]/EXTI15/5VT24VSS3325P2_3/MCPWM1_CH2P/TIM1_CH1/CAN_TX/EFLS_DAT[3]26P2_4/MCPWM1_CH1P/TIM2_CH0/CAN_RX/EFLS_CSN27P2_5/MCPWM1_CH0P/UART1_RXD/TIM1_CH0/TIM2_CH1/CAN_TMR/EFLS_CLK28P2_6/MCPWM1_CH2N/UART1_TXD/TIM1_CH129P2_7/MCPWM1_CH1N/SDA0/TIM2_CH0/EXTI1630P2_8/MCPWM1_CH0N/SCL0/TIM2_CH1/EXTI1731P2_9/MCPWM0_CH2P/SDA0/TIM4_CH1/TIM2_Z/EFLS_DAT[0]32P2_10/MCPWM0_CH1P/SCL0/TIM4_CH0/EFLS_DAT[1]33P2_11/MCPWM0_CH0P/UART0_RXD/TIM4_CH0/TIM3_CH1/EFLS_DAT[2]/5VT34P2_12/MCPWM0_CH2N/UART0_TXD/TIM4_CH1/TIM3_Z/EFLS_DAT[3]/EXTI18/5VT35P2_13/HALL0_IN2/MCPWM0_CH1N/TIM4_CH0/TIM3_CH0/ADC_TRIGGER1/EFLS_CSN36P2_14/HALL0_IN1/MCPWM0_CH0N/UART2_TXD/TIM3_CH1/ADC_TRIGGER0/CMP3_IN/WAKE637P2_15/CMP3_OUT/HALL0_IN0/MCPWM0_BKIN0/UART2_RXD/TIM1_CH0/EFLS_CLK/CMP3_IP0/EXTI19/5VT38P3_1/HALL1_IN1/MCPWM0_BKIN3/SDA0/TIM0_Z/TIM3_CH0/ADC0_CH13/CMP3_IP2/5VT39P3_2/CMP3_OUT/HALL1_IN0/SCL0/TIM0_CH0/TIM3_CH0/EFLS_DAT[0]/CMP3_IP3/WAKE7/EXTI20/5VT40VSS41P3_3/CMP2_OUT/SPI0_CSN/TIM0_CH1/EFLS_DAT[1]/ADC1_CH13/CMP2_IP0/EXTI2142P3_4/HALL0_IN0/SPI0_CLK/TIM1_CH1/EFLS_DAT[2]/ADC1_CH12/DAC0_OUT/CMP2_IP1/5VT43P3_5/HALL0_IN1/MCPWM1_BKIN2/UART1_RXD/SPI0_DO/TIM1_CH0/CAN_TMR/EFLS_DAT[3]/ADC1_CH11/CMP2_IP2/5VT44P3_6/HALL0_IN2/MCPWM1_BKIN3/UART1_TXD/SPI0_DI/TIM1_CH1/ADC_TRIGGER2/CAN_TX/EFLS_CSN/CMP2_IP3/5VT45P3_7/CMP2_OUT/MCPWM1_BKIN0/TIM4_CH1/ADC_TRIGGER1/CAN_RX/OPA3_IN/ADC2_CH11/CMP2_IN/EXTI2246P3_8/MCPWM1_BKIN1/TIM4_CH0/ADC_TRIGGER0/EFLS_CLK/OPA3_IP/ADC2_CH10/EXTI2347P3_9/MCPWM0_BKIN0/TIM0_CH1/OPA2_IN/ADC2_CH948P3_10/MCPWM0_BKIN1/OPA2_IP/ADC2_CH849P3_11/MCPWM0_BKIN2/ADC2_CH7/OPAx_OUT0/REF/EXTI2450P3_12/MCPWM0_BKIN3/SDA0/TIM2_CH1/ADC2_CH6/EXTI2551P3_13/OPA1_IN/ADC2_CH5/EXTI2652P3_14/OPA1_IP/ADC2_CH4/EXTI2753P4_13/CMP0_OUT/HALL0_IN2/SPI1_CLK/SCL0/TIM1_Z/TIM2_Z/CAN_TX/EFLS_DAT[0]/ADC0_CH10/CMP0_IP154P4_14/CLK/HALL0_IN1/UART2_TXD/SPI1_DO/SDA0/TIM1_CH1/TIM2_CH0/ADC_TRIGGER2/CAN_RX/EFLS_DAT[1]/ADC0_CH9/CMP0_IP2/5VT55P4_5/MCPWM0_CH1P/ADC0_CH11/CMP0_IP0/5VT56P4_6/MCPWM0_CH1N/EFLS_CLK/ADC1_CH8/OPAx_OUT1/LDO1257P4_7/ADC1_CH7/DAC1_OUT58P4_8/CLK/ADC1_CH6/CMP1_IN/P4_9/CMP1_OUT/TIM3_CH1/CMP1_IP0/5VT59AVDD60AVDD61VSS3362P4_15/HALL0_IN0/UART2_RXD/SPI1_D1/SCL0/TIM1_CH0/TIM2_CH1/ADC_TRIGGER1/CAN_TMR/EFLS_DAT[2]/ADC0_CH8/CMP0_IP3/5VT63P5_0/CMP0_OUT/MCPWM0_CH3N/SDA1/TIM3_CH0/ADC_TRIGGER0/EFLS_DAT[3]/ADC0_CH7/CMP0_IN/EXTI3264